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LH51BV1000J
FEATURES * Access time: 70 ns (MAX.) * Current consumption: Operating: 30 mA (MAX.) 5 mA (MAX.) (tRC, tWC = 1 s) Standby: 60 A (MAX.) * Data Retention: 1.0 A (MAX.) (VCCDR = 3 V, TA = 25C) * Single power supply: 2.7 V to 3.6 V * Operating temperature: -25C to +85C * Fully-static operation * Three-state output * Not designed or rated as radiation hardened * Package: 32-pin 6 x 10 mm CSP * N-type bulk silicon DESCRIPTION
The LH51BV1000JY is a static RAM organized as 131,072 x 8 bits which provides low power standby mode. It is fabricated using silicon-gate CMOS process technology.
A B C D E F
CMOS 1M (128K x 8) Static Ram
PIN CONNECTIONS
1
A2 I/O1 GND I/O4 I/O7 A10
2
A3 A0 I/O3 I/O5
3
A1 I/O2
4
5
6
NC A12
7
A4 A6 A14 A15
8
A5 A7 A16 VCC WE A9
I/O8 I/O6 OE CE1
CE2 A8
A13 A11
51BV1000-1
Figure 1. Pin Connections for CSP Package
1
LH51BV1000J
CMOS 1M (128K x 8) Static RAM
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 ADDRESS BUFFER
VCC GND 10 1024 ROW DECODER MEMORY CELL ARRAY (1024 x 128 x 8)
128 x 8 7 COLUMN DECODER 128
COLUMN GATE
8 CE1, CE2 CONTROL LOGIC
CE1 CE2
WE OE
OE, WE CONTROL LOGIC
I/O BUFFER
I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8
51BV1000-2
Figure 2. LH51BV1000JY Block Diagram
PIN DESCRIPTION
SIGNAL PIN NAME SIGNAL PIN NAME
A0 - A16 CE1 CE2 WE OE
Address inputs Chip enable 1 Chip enable 2 Write enable Output enable
I/O1 - I/O8 VCC GND NC
Data inputs and outputs Power supply Ground No connection
TRUTH TABLE
CE1 CE2 WE OE MODE I/O1 - I/O8 SUPPLY CURRENT
H L L L
L H H H
L H H
L H
Standby Standby Write Read Output disable
High impedance High impedance Data input Data output High impedance
Standby (ISB) Standyby (ISB) Active (ICC) Active (ICC) Active (ICC)
NOTE: 1. = Don't care, L = Low, H = High
2
CMOS 1M (128K x 8) Static RAM
LH51BV1000J
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT NOTE
Supply voltage Input voltage Operating temperature Storage temperature
VCC VIN TOPR TSTG
- 0.5 to +4.6 - 0.5 to VCC + 0.3 - 25 to +85 - 65 to +150
V V C C
1 1, 2
NOTE: 1. The maximum applicable voltage on any pin with respect to GND. 2. Undershoot of -3.0 V is allowed width of pulse below 50 ns.
RECOMMENDED OPERATING CONDITIONS (TA = -25C to +85C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE
Supply voltage Input voltage
VCC VIH VIL
2.7 2.2 -0.3
3.0
3.6 VCC + 0.3 0.4
V V V
1
NOTE: 1. Undershoot of -3.0 V is allowed width of pulse below 50 ns.
DC ELECTRICALCHARACTERISTICS (TA = -25C to +85C, VCC = 2.7 V to 3.6 V)
PARAMETER SYMBOL CONDITIONS MIN. TYP.1 MAX. UNIT
Input leakage current Output leakage current Operating supply current
ILI ILO ICC1 ICC2
VIN = 0 V to VCC CE1 = VIH or CE2 = VIL or OE = VIH or WE = VIL VI/O = 0 V to VCC CE1 = VIL, VIN = VIL or VIH CE2 = VIH, II/O = 0 mA CE1 = VIL, VIN = VIL or VIH CE2 = VIH, II/O = 0 mA CE1 = V IH or CE2 = VIL IOL = 2.0 mA, VCC 3 V IOL = -0.1 mA IOH = - 2. 0 m A, V CC 3 V IOH = -0.1 mA tCYCLE = MIN. tCYCLE = 1.0 s
-1.0 -1.0 2.4 VCC - 0.2
0.6
1.0 1.0 30
A A
mA 5 60 1.0 0.4 0.2 V A mA
Standby current
ISB ISB1 VOL
CE1, CE2 VCC - 0.2 V or CE2 0.2 V
Output voltage VOH
NOTE: 1 Typical values at VCC = 5.0 V, TA = 25C
AC ELECTRICAL CHARACTERISTICS AC Test Conditions
PARAMETER MODE NOTE
Input pulse level Input rise and fall time Input and output timing ref. level Output load
NOTE: 1. Including scope and jig capacitance.
0.4 V to 2.4 V 5 ns 1.5 V 1 TTL + CL (100 pF)
1
3
LH51BV1000J
CMOS 1M (128K x 8) Static RAM
READ CYCLE (TA = -25C to +85C, VCC = 2.7 V to 3.6 V)
PARAMETER SYMBOL MIN. MAX. UNIT NOTE
Read cycle time Address access time CE 1 access time CE 2 access time Output enable to output valid Output hold from address change CE 1 Low to output active CE 2 High to output active OE Low to output active CE 1 High to output in High impedance CE 2 Low to output in High impedance OE High to output in High impedance
tRC tAA tACE1 tACE2 tOE tOH tLZ1 tLZ2 tOLZ tHZ1 tHZ2 tOHZ
70 10 5 5 0
70 70 70 40 30 30 30
ns ns ns ns ns ns ns ns ns ns ns ns
1 1 1 1 1 1
NOTE: 1. Active output to High impedance to output active tests specified for a 200 mV transition from steady state levels into the test load.
WRITE CYCLE (TA = -25C to +85C, VCC = 2.7 V to 3.6 V)
PARAMETER SYMBOL MIN. MAX. UNIT NOTE
Write cycle time Chip enable to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Input data setup time Input data hold time WE High to output active WE Low to output in High impedance OE High to output in High impedance
tWC tCW tAW tAS tWP tWR tDW tDH tOW tWZ tOHZ
70 60 60 0 55 0 30 0 5
30 30
ns ns ns ns ns ns ns ns ns ns ns
1 1 1
NOTE: 1. Active output to High impedance to output active tests specified for a 200 mV transition from steady state levels into the test load.
4
CMOS 1M (128K x 8) Static RAM
LH51BV1000J
DATA RETENTION CHARACTERISTICS (TA = -25C to +850C)
PARAMETER SYMBOL CONDITIONS MIN. TYP.1 MAX. UNIT NOTES
Data retention supply voltage
VCCDR
CE2 0.2 V or CE1 VCCDR - 0.2 V VCCDR = 3 V CE2 0.2 V or CE1 VCCDR - 0.2 V TA = 25C TA = 40C
2.0
0.5
3.6 1.0 3.0 50
V A A ms
2 2
Data retention supply current
ICCDR
Chip enable setup time Chip enable hold time
tCDR

0
tR
5
ms
NOTES: 1. Typical value at TA = 25C 2. CE2 VCCDR - 0.2 V or CE2 0.2 V
PIN CAPACITANCE (TA = 25C, f = 1 MHz)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE
Input capacitance I/O capacitance
CIN CI/O
VIN = 0 V VI/O = 0 V

8 10
pF pF
1 1
NOTE: 1. This parameter is sampled and not production tested.
5
LH51BV1000J
CMOS 1M (128K x 8) Static RAM
tRC
ADDRESS tAA tACE1
CE1 tLZ1 tHZ1
CE2 tLZ2 tACE2 tOE tHZ2
OE tOLZ tOHZ tOH
DOUT NOTE: WE is HIGH for Read cycle.
DATA VALID
51BV1000-3
Figure 3. Read Cycle
6
CMOS 1M (128K x 8) Static RAM
LH51BV1000J
tWC
ADDRESS
OE tAW tCW
(NOTE 2)
(NOTE 4)
tWR
CE1 tCW
(NOTE 2)
tWR
CE2 tAS
(NOTE 3)
tWP
(NOTE 1)
tWR
WE tOHZ
(NOTE 6)
DOUT tDW
(NOTE 5)
tDH
DIN NOTES: 1. A write occurs during the overlap of a LOW CE1, a HIGH CE2 and a LOW WE, A write begins at the latest transition among CE1 going LOW, CE2 going HIGH and WE going LOW. A write ends at the earliest transition among CE1 going HIGH, CE2 going LOW and WE going HIGH. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the latter of CE1 going LOW or CE2 going HIGH to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR1 applies in case a write ends at CE1 or WE going HIGH. tWR2 applies in case a write ends at CE2 going LOW. 5. During this period, I/O pins are in the output state, therefore the input signals of opposite phase to the outputs must not be applied. 6. If CE1 goes LOW simultaneously with WE going LOW or after WE going LOW, the outputs remain in high impedance state. 7. If CE1 goes HIGH simulaneously with WE going HIGH or before WE going HIGH, the outputs remain in high impedance state.
DATA VALID
51BV1000-4
Figure 4. Write Cycle (OE Controlled)
7
LH51BV1000J
CMOS 1M (128K x 8) Static RAM
tWC
ADDRESS tAW tCW
(NOTE 2)
tWR
(NOTE 4)
CE1 tCW
(NOTE 2)
tWR
CE2 tAS
(NOTE 3)
tWP
(NOTE 1)
tWR
WE tWZ tOW
(NOTE 7)
(NOTE 6)
DOUT tDW DIN
(NOTE 5)
tDH
DATA VALID
NOTES: 1. A write occurs during the overlap of a LOW CE1, a HIGH CE2 and a LOW WE, A write begins at the latest transition among CE1 going LOW, CE2 going HIGH and WE going LOW. A write ends at the earliest transition among CE1 going HIGH. CE2 going LOW and WE going HIGH. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the latter of CE1 going LOW or CE2 going HIGH to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR1 applies in case a write ends at CE1 or WE going HIGH. tWR2 applies in case a write ends at CE2 going LOW. 5. During this period, I/O pins are in the output state, therefore the input signals of opposite phase to the outputs must not be applied. 6. If CE1 goes LOW simultaneously with WE going LOW or after WE going LOW, the outputs remain in high impedance state. 7. If CE1 goes HIGH simulaneously with WE going HIGH or before WE going HIGH, the outputs remain in high impedance state.
51BV1000-5
Figure 5. Write Cycle (OE Low Fixed)
8
CMOS 1M (128K x 8) Static RAM
LH51BV1000J
CE1 CONTROL (NOTE)
DATA RETENTION MODE VCC 2.7 V 2.2 V VCCDR CE1 VCCDR - 0.2 V CE1 0V CE2 CONTROL tCDR tR
DATA RETENTION MODE VCC 2.7 V CE2 VCCDR 0.4 V tCDR tR
0V CE2 0.2 V NOTE: To control the data retention mode at CE1, fix the input level of CE2 between VCCDR and VCCDR - 0.2 V or 0 V and 0.2 V during the data retention mode.
51BV1000-6
Figure 6. Data Retention Chart (CE1 Controlled)
9
LH51BV1000J
CMOS 1M (128K x 8) Static RAM
PACKAGE DIAGRAM
32CSP (FBGA032-P-0610) B A
INDEX TOP VIEW
10.20 [0.402] 10.00 [0.394]
6.20 [0.244] 6.00 [0.236]
0.10 [0.004] S
S
SIDE VIEW
DETAIL
0.30 [0.012] TYP. (NOTE)
0.67 [0.026] TYP. 0.20 [0.008] MIN. 1.20 [0.047] MAX.
32CSP
(See Detail) 0.10 [0.004] S 0.80 [0.031] TYP. 1.20 [0.047] TYP.
C
BOTTOM VIEW
D
0.80 [0.031] TYP. 0.40 [0.016] TYP.
0.35 [0.014] NOTE: Land hole diameter for ball mounting. DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT
0.30 [0.012] M 0.15 [0.006] M
S S
AB CD
10
CMOS 1M (128K x 8) Static RAM
LH51BV1000J
ORDERING INFORMATION
LH51BV1000J Device Type Y Package - ## Speed LL Power Low-Low power standby 70 ns Access Time (ns) 32-pin, 6 x 10 mm CSP (FBGA032-P-0610) CMOS 1M (124K x 8) Static RAM Example: LH51BV1000JY-70LL (CMOS 1M (124K x 8) Static RAM, 70 ns, Low-Low power standby, 32-pin CSP)
51BV1000-7
11

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